Anne Arundel Community College

Arnold, Maryland

Fall 2009
Date last modified: 11/29/2009

  

 

 

Course Descriptions

This course presents fundamental logic units and techniques needed in hardware design of digital systems including gates, flip-flops, registers and counters. Karnaugh map simplification of gate networks, switching algebra, synchronous sequential systems, PLAs and elements of binary arithmetic units. This course is required for second-year students planning to major in electrical (or computer) engineering.

Learning Objectives

 

        All students will

1. Articulate the differences between analog and digital systems along with advantages and disadvantages of each.
2. Convert between and manipulate quantities on the numbers systems common to digital systems (binary, hexadecimal, BCD, and decimal).
3. Describe and use common digital logic gates.
4. Derive logical expressions to model real-world situations.
5. Reduce Boolean expressions to simplest form.
6. Construct combinational circuits that model desired behaviors.
7. Explain the behavior of latches and flip-flops (bi-stable memory elements).
8. Use flip-flops to design and construct synchronous and asynchronous counters and registers.
9. Select appropriate medium scale integration (MSI) chips to perform specified    within a digital system.
10. Recognize the basic forms of hardware descriptive language (HDL).
11. Discuss advantages of using HDL compared to discrete logic gates.
12. Illustrate uses of analog-to-digital (ADC) and digital-to-analog (DAC) conversion.
13. Design simple sequential, combinational logic systems that use ADC and/or DAC to communicate with the real world.
14. Perform the roles of engineers and technicians (as appropriate) in a typical technical workplace.
15. Record laboratory experiences and communicate the purpose, procedures and results, concisely and accurately, in a technical manner.
16. Use computer-based applications to create and verify digital designs.
17. Describe the logical functioning of digital components and systems through the use of VHDL.
18. Download digital designs into Complex Programmable Logic Devices (CPLD) or Field-Programmable Gate Arrays (FPGA)and ascertain the correctness of the solution.

Required Textbook

 

Digital Systems,10^th ed., Tocci, Widmer & Moss (with CDROM)

Class Procedures

 

Class will normally consist of classroom discussion followed by lab exercises. This routine may be reversed. All students will turn-in homework at the beginning of class, then any requested problems will be worked. Labs will be completed individually as there are sufficient labs stations for each student to have their own.

 

Lab Notebooks

Lab activities will be recorded in a bound lab notebook. This includes are prepared labs provided by your instructor. As a professional it is vital that you know how to record lab setup, procedures, results and conclusions in an organized manner. This practice is a common requirement for your employment and for using a lab facility, and may be considered a legal document. This specific guidance had been developed at the Rochester Institute of Technology following procedures used by the Eastman Kodak Company. Please print a copy to use as reference.

Grading
 

All grading will be on a point basis. You will receive the course grade based upon how many points you earn, as long as:

1. You have greater than a 70% test/exam average AND
2. You pass the lab practical exams
    

There are 14 weeks worth of homework, labs and lab reports.

There are 2 midterm exams and 1 lab practical.

The final exam will be given as per the schedule of classes.

 
An Excel worksheet for points earned and grades is available.

Dates

Fall Term 2009

August 24	All 15-week session classes, TV, distance and first 8-week session classes begin
September 4	No classes after 4:30 p.m. (Labor Day Break)
September 5-7	Labor Day Break (no classes)
November 2	Deadline for submitting application for December 2009 graduation
November 16	Last day to withdraw from a class with a "W" grade (15 and 13-week session classes)
November 25	No classes after 4:30 p.m. (Thanksgiving Break)
November 26-29	Thanksgiving Break (no classes)
December 6	15-week and 13-week session classes end
December 7-13	Final exams (13 and 15-week session classes)

Student  Absences and Lateness

 

Although sickness and unforeseen circumstances may preclude one from attending class or being on time, this should not be the norm. A professional is where they need to be and prepared to begin work as scheduled. Repeated absences or lateness will normally be reflected not only in missed/late assignments, but may also hinder learning of required material and thus lower test grades. Assignments that are due at the beginning of class are due at that time, not when you may get to class. Bottom line: be here on time and ready to work.

Special Accommodation

 

Students who have need for special accommodation due to a physical or learning disability should contact the Office of Disabled Services at (410) 777-2307. Please refer to the current college catalog for more information.

 

Academic Regulations.  Please refer to current college catalog.

Academic Integrity Policy

 

“All students are required to exhibit academic honesty in all academic exercises and assignments”. The full text is available in the current college catalog and on the AACC  website. In addition, you are being provided with a printed copy for your use.

 

All assignments are to be considered as individual unless expressly directed otherwise.

 

You should specifically know that violations of the college policy on cheating might result in any of the following:

1. The instructor may issue a failing grade on an assignment or a test.
2. The instructor may issue a failing grade in a course.
3. The instructor may file charges with the Committee on Discipline leading to possible reprimand, probation, suspension, or expulsion form the college.

Computer and Electronic Communication Access and Usage at AACC

 

Please refer to the current college catalog. You should consider use of the electronics labs and computers subject to the same general lab policy as any other lab in this school.

Student Conduct Code

 

Details are contained in the current college catalog. However, in essence, anything that interrupts or distracts from the learning experience in the classroom or in the laboratory will not be allowed and will be dealt with as addressed by the college policy.

Use of cell phones is not permitted in either lecture or lab or in the hallway close enough to be heard in the classroom.  Cell phones and pagers should be turned off or set to vibrate only.  Cell phones may not be answered in the classroom or lab.   

No tobacco products (smoking or chewing tobacco) may be used in any classes.  Food and drinks are prohibited in the lab.

Course Schedule                                                                  

 

Week Monday	Topic	Read (Tocci)	Homework Problems	Labs (May be passworded)
1 8/24	Introduction Number Systems and Codes	Chapter 1 Chapter 2 (no octal)	1-1, 1-4, 1-7, 1-10 2-1, 2-5, 2-11, 2-13, 2-19	1 2, 3
2 8/31	Describing Logic Circuits   Hardware Description Languages	3-1 through 3-16   3-17 and 3-20	3-1, 3-6, 3-9, 3-12, 3-15   3-26, 3-32, 3-38, 3-40	4 Multisim    Altera
3 9/7	----   Combinational Logic Circuits Exclusive OR/NOR, Parity	----   4-1 through 4-5 4-6 through 4-8	---- 4-1, 4-2, 4-4, 4-5, 4-20, 4-21, 4-26	No class on Monday 26 K-Map Minimizer
4 9/14	Characteristics/Troubleshooting,  Review   Test 1  Guidance  (No lab today)	4-9 through 4-13	4-34, 4-39, 4-41, 4-47 All HW is due!
5 9/21	HDL     Programmable Logic Devices	3-17 through 3-20   4-14 through 4-17	3-43, 3-45, 3-48     4-50, 4-56, 4-57, 4-58
6 9/28	Flip-Flops	5-1 through 5-9 RSFF animation	5-3, 5-6, 5-7, 5-9, 5-13	8   9 (use bdf & VHDL) VHDL FF’s (ref)
7 10/5	Data storage/transfer     Frequency Division &  Clocks	5-17 through 5-18   5-19 through 5-24 555 Simulator	5-27, 5-28, 5-29, 5-32, 5-33, 5-34, 5-35, 5-39, 5-41, 5-45	10
8 10/12	Arithmetic Operations and Circuits	6-1 through 6-8 6-9 through 6-14	5-46, 5-49, 5-50, 5-53, 5-54, 6-1, 6-2, 6-4, 6-9, 6-11	Multivibrator Lab 23
9 10/19	Test 2 (No lab today)   Introduction to Counters		6-15, 6-18, 6-19, 6-20 All HW is due!
10 10/26	Counters   Synchronous Counter Design	7-1 through 7-9 7-10	7-1, 7-2, 7-3, 7-4, 7-5, 7-8, 7-14, 7-36, 7-44	11 14
11 11/2	Series/Parallel/Shift Registers	7-15 through 7-21	Sequential Counter Exercise	Parallel In/Serial Out Lab
12 11/9	IC Logic Families MSI Circuits 1	8-1 through 8-10 9-1 through 9-9	8-1, 8-3, 8-6, 8-7, 8-15, 9-1, 9-2, 9-8, 9-12, 9-27, 9-29, 9-37
13 11/16	D/A Conversion	11-1 through 11-6	11-1, 11-2, 11-3, 11-4, 11-6	DAC Lab DAC with 741
14 11/23	A/D Conversion Memory	11-8 through 11-12 12-1 through 12-14	11-24, 11-30, 11-33	ADC Lab RAM Lab
15 11/31	Lab Practical Exam Review and Course Critique		None	Surprise
Final Exam	Final Exam Wednesday, December 9th 2:45 -- 4:45      CALT 309	Chapters 7 - 12	Past Exams: EGR244 Exam 1 Fall 2006 EGR244 Exam 2 Fall 2004 EGR244 Exam 3 Fall 2004 EGR244 Exam 3 Spring 2007 EGR244 Final Exam Spring 2005 EGR244 Final Exam Fall 2006 ENEE244 Practice Midterm Spring 2001 ENEE244 Practice Final Spring 2001